/*
* Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Description:
* Author: huawei
* Create: 2019-10-15
*/

#ifndef __DMS_NODE_TYPE_H__
#define __DMS_NODE_TYPE_H__

typedef enum {
    DMS_DEV_TYPE_SOC = 0X40,
    DMS_DEV_TYPE_PCIE_LINK = 0X41,
    DMS_DEV_TYPE_HCCS_LINK = 0X42,
    DMS_DEV_TYPE_CPU_CORE = 0X50,
    DMS_DEV_TYPE_L3D = 0X51,
    DMS_DEV_TYPE_L3T = 0X52,
    DMS_DEV_TYPE_MESH = 0X53,
    DMS_DEV_TYPE_RING = 0X54,
    DMS_DEV_TYPE_RBRG = 0X55,
    DMS_DEV_TYPE_GIC = 0X56,
    DMS_DEV_TYPE_ITS = 0X57,
    DMS_DEV_TYPE_MN = 0X58,
    DMS_DEV_TYPE_CS = 0X59,
    DMS_DEV_TYPE_SIOE = 0X5A,
    DMS_DEV_TYPE_SLLC = 0X5B,
    DMS_DEV_TYPE_PCIE = 0X5C,
    DMS_DEV_TYPE_ROCE = 0X5D,
    DMS_DEV_TYPE_NIC = 0X5E,
    DMS_DEV_TYPE_UFS = 0X5F,
    DMS_DEV_TYPE_SPI = 0X60,
    DMS_DEV_TYPE_XGMAC = 0X61,
    DMS_DEV_TYPE_SAFETYISLAND = 0X62,
    DMS_DEV_TYPE_TS = 0X63,
    DMS_DEV_TYPE_AIC = 0X64,
    DMS_DEV_TYPE_AIV = 0X65,
    DMS_DEV_TYPE_L2BUF = 0X66,
    DMS_DEV_TYPE_SDMA = 0X67,
    DMS_DEV_TYPE_DVPP = 0X68,
    DMS_DEV_TYPE_JPEGD = 0X69,
    DMS_DEV_TYPE_JPEGE = 0X6A,
    DMS_DEV_TYPE_PNGD = 0X6B,
    DMS_DEV_TYPE_VDEC = 0X6C,
    DMS_DEV_TYPE_VENC = 0X6D,
    DMS_DEV_TYPE_VPC = 0X6E,
    DMS_DEV_TYPE_DDR = 0X6F,
    DMS_DEV_TYPE_HBM = 0X70,
    DMS_DEV_TYPE_LPM = 0X71,
    DMS_DEV_TYPE_HSM = 0X72,
    DMS_DEV_TYPE_SAFE_SEC = 0X73,
    DMS_DEV_TYPE_GPU = 0X74,
    DMS_DEV_TYPE_DISPLAY = 0X75,
    DMS_DEV_TYPE_AUDIO = 0X76,
    DMS_DEV_TYPE_CAMERA = 0X77,
    DMS_DEV_TYPE_DDRA = 0X78,
    DMS_DEV_TYPE_HBMA = 0X79,
    DMS_DEV_TYPE_ISP = 0X7A,
    DMS_DEV_TYPE_HWTS_S_TS = 0X7B,
    DMS_DEV_TYPE_BASE_SERVCIE = 0X7C,
    DMS_DEV_TYPE_TSCPU = 0X7D,
    DMS_DEV_TYPE_TSD_DAEMON = 0X7E,
    DMS_DEV_TYPE_DMP_DAEMON = 0X7F,
    DMS_DEV_TYPE_ADDA = 0X80,
    DMS_DEV_TYPE_SLOGD = 0X81,
    DMS_DEV_TYPE_LOG_DAEMON = 0X82,
    DMS_DEV_TYPE_PORT = 0X83,
    DMS_DEV_TYPE_CAN = 0X84,
    DMS_DEV_TYPE_SENSORHUB = 0X85,
    DMS_DEV_TYPE_MCU = 0X86,
    DMS_DEV_TYPE_OPP_SOC = 0X87,
    DMS_DEV_TYPE_PMU = 0X88,
    DMS_DEV_TYPE_VR = 0X89,
    DMS_DEV_TYPE_MBIGEN = 0X8A,
    DMS_DEV_TYPE_TEE_OS = 0X8B,
    DMS_DEV_TYPE_AO_SUBSYS = 0X8C,
    DMS_DEV_TYPE_PERI_SUBSYS = 0X8D,
    DMS_DEV_TYPE_HAC_SUBSYS = 0X8E,
    DMS_DEV_TYPE_IO_SUBSYS = 0X8F,
    DMS_DEV_TYPE_HILINK = 0x90,
    DMS_DEV_TYPE_MEDIA_SUB_SYS = 0x91,
    DMS_DEV_TYPE_ISP_SUB_SYS = 0x92,
    DMS_DEV_TYPE_CPU_CLUSTER = 0X93,
    DMS_DEV_TYPE_HWTSCPU = 0x96,
    DMS_DEV_TYPE_TSFW = 0x97,
    DMS_DEV_TYPE_DSA = 0x98,
    DMS_DEV_TYPE_TS_DISP = 0X99,
    DMS_DEV_TYPE_TS_AA = 0X9A,
    DMS_DEV_TYPE_TS_SCHE = 0X9B,
    DMS_DEV_TYPE_TS_SMMU = 0X9C,
    DMS_DEV_TYPE_AIC_DISP = 0x9D,
    DMS_DEV_TYPE_AIC_AA = 0X9E,
    DMS_DEV_TYPE_AIC_SMMU = 0X9F,
    DMS_DEV_TYPE_AIV_DISP  = 0XA0,
    DMS_DEV_TYPE_AIV_AA = 0XA1,
    DMS_DEV_TYPE_AIV_SMMU = 0XA2,
    DMS_DEV_TYPE_DVPPSUB_DISP = 0xA3,
    DMS_DEV_TYPE_DVPPSUB_AA = 0xA4,
    DMS_DEV_TYPE_DVPPSUB_SCHE = 0xA5,
    DMS_DEV_TYPE_DVPPSUB_SMMU = 0xA6,
    DMS_DEV_TYPE_ISPSUB_DISP = 0xA7,
    DMS_DEV_TYPE_ISPSUB_AA = 0xA8,
    DMS_DEV_TYPE_ISPSUB_SCHE = 0xA9,
    DMS_DEV_TYPE_ISPSUB_SMMU = 0xAA,
    DMS_DEV_TYPE_AOSUB_DISP = 0xAB,
    DMS_DEV_TYPE_AOSUB_AA = 0xAC,
    DMS_DEV_TYPE_AOSUB_SCHE = 0xAD,
    DMS_DEV_TYPE_AOSUB_SMMU = 0xAE,
    DMS_DEV_TYPE_PERI_DISP = 0xAF,
    DMS_DEV_TYPE_PERI_AA = 0xB0,
    DMS_DEV_TYPE_PERI_SCHE = 0xB1,
    DMS_DEV_TYPE_PERI_SMMU = 0xB2,
    DMS_DEV_TYPE_HAC_DISP = 0xB3,
    DMS_DEV_TYPE_HAC_AA = 0xB4,
    DMS_DEV_TYPE_HAC_SCHE = 0xB5,
    DMS_DEV_TYPE_HAC_SMMU = 0xB6,
    DMS_DEV_TYPE_IO_DISP = 0xB7,
    DMS_DEV_TYPE_IO_AA = 0xB8,
    DMS_DEV_TYPE_IO_SCHE = 0xB9,
    DMS_DEV_TYPE_IO_SMMU = 0xBA,
    DMS_DEV_TYPE_SILS_DISP = 0xBB,
    DMS_DEV_TYPE_SILS_AA = 0xBC,
    DMS_DEV_TYPE_SILS_SCHE = 0xBD,
    DMS_DEV_TYPE_SILS_SMMU = 0xBE,
    DMS_DEV_TYPE_POWER_GLITCH_SENSOR = 0xC8,
    DMS_DEV_TYPE_DSA_DISP = 0xC9,
    DMS_DEV_TYPE_NIC_DISP = 0xCA,
    DMS_DEV_TYPE_PCIE_DISP = 0xCB,
    DMS_DEV_TYPE_HCCS = 0xCD,
    DMS_DEV_TYPE_EMMC = 0xCE,
    DMS_DEV_TYPE_MAX,
} DMS_DEVICE_NODE_TYPE;

typedef enum {
    DMS_DEV_NODE0 = 0x0,
    DMS_DEV_NODE1 = 0x1,
    DMS_DEV_ID_MAX
} DMS_DEVICE_NODE_ID;

typedef enum {
    HAL_DMS_DEV_TYPE_BASE_SERVCIE = 0x600,
    HAL_DMS_DEV_TYPE_PROC_MGR = 0x601,
    HAL_DMS_DEV_TYPE_IAMMGR = 0x602,
    HAL_DMS_DEV_TYPE_PROC_LAUNCHER = 0x603,
    HAL_DMS_DEV_TYPE_ADDA = 0x604,
    HAL_DMS_DEV_TYPE_DMP_DAEMON = 0x605,
    HAL_DMS_DEV_TYPE_SKLOGD = 0x606,
    HAL_DMS_DEV_TYPE_SLOGD = 0x607,
    HAL_DMS_DEV_TYPE_LOG_DAEMON = 0x608,
    HAL_DMS_DEV_TYPE_HDCD = 0x609,
    HAL_DMS_DEV_TYPE_AICPU_SCH = 0x60B,
    HAL_DMS_DEV_TYPE_QUEUE_SCH = 0x60C,
    HAL_DMS_DEV_TYPE_AICPU_CUST_SCH = 0x60E,
    HAL_DMS_DEV_TYPE_HCCP = 0x60F,
    HAL_DMS_DEV_TYPE_TSD_DAEMON = 0x610,
    HAL_DMS_DEV_TYPE_TIMER_SERVER = 0x616,
    HAL_DMS_DEV_TYPE_OS_LINUX = 0x617,
    HAL_DMS_DEV_TYPE_DATA_MASTER = 0x619,
    HAL_DMS_DEV_TYPE_CFG_MGR = 0x61A,
    HAL_DMS_DEV_TYPE_DATA_GW = 0x61D,
    HAL_DMS_DEV_TYPE_MAX
} HAL_DMS_DEVICE_NODE_TYPE;

/* bit 15~8: 000-hardware/kernel 110-soft 111-product */
#define DMS_EVENT_OBJ_KERNEL (0x0)
#define DMS_EVENT_OBJ_USER (0x6)
#define DMS_EVENT_OBJ_PRODUCT (0x7)
#define DMS_EVENT_OBJ_TYPE(node_type) (((node_type) >> 8) & 0x7)

int dms_get_node_type_str(unsigned short node_type, char *node_str, unsigned int str_len);
int dms_check_node_type(int node_type);

#endif
